1. Field of the Invention
The present invention is directed in general to integrated circuit devices and methods for manufacturing same. In one aspect, the present invention relates to the manufacture and use of lateral double diffusion MOS transistor (LDMOSFET) devices.
2. Description of the Related Art
High-voltage integrated circuits applications, such as high-voltage smart power applications, are constructed with integrated circuit MOS field effect transistor devices which must be able to sustain high voltages (e.g., fifty volts or greater) across the transistor device's source, body, gate, and drain terminals. With such high-voltage applications, lateral double diffusion MOS (LDMOS) transistor devices are often used to provide the high-voltage transistor devices. But such LDMOS devices usually require thick and low-doped epitaxial layer, which makes them difficult to integrate with low-voltage circuitry on the same chip. In addition, there are typically tradeoffs posed when integrating LDMOS devices between the on-resistance and breakdown voltage parameters of such devices, where the on-resistance is ideally kept low and the breakdown voltage is ideally kept high. For example, a design for an LDMOS device which increases the device breakdown voltage typically also increases the on-resistance, which is undesirable. There are additional challenges presented with LDMOS devices, include the problem of parasitic substrate injection into the substrate in certain situations and the degradation of the safe operating area (SOA) which is the voltage and current conditions over which the device can be expected to operate without self-damage (e.g., the maximum drain current for a given drain voltage).
Accordingly, a need exists for improved semiconductor devices, especially RESURF type semiconductor devices having improved substrate injection suppression and increased safe operating area, without a corresponding degradation of other important device properties. There is also a need for a high-voltage transistor device and fabrication processes to overcome the problems in the art, such as outlined above. Further limitations and disadvantages of conventional processes and technologies will become apparent to one of skill in the art after reviewing the remainder of the present application with reference to the drawings and detailed description which follow.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements for purposes of promoting and improving clarity and understanding. Further, where considered appropriate, reference numerals have been repeated among the drawings to represent corresponding or analogous elements.